A conventional bipolar junction transistor 10 is depicted in FIG. 1. The device is formed on a silicon substrate 12 which is illustratively P.sup.- type. A buried N.sup.+ layer 14 is located on the substrate 12 and an N-type collector region 16 is located on buried N.sup.+ layer 14. In addition, a plurality of field oxide (FOX) regions 18 are formed on the substrate. An N.sup.+ deep connection region 20 connects the substrate surface to the buried N.sup.+ layer 14 to form a collector contact to collector 16. A P-type base region 22 is formed in the N-type well 16, which forms the collector. Two P.sup.+ -type base contact regions 24 and 26 are formed on either side of the base 22.
The emitter 28 includes the N.sup.+ polysilicon or polycide region 30 formed on the surface of the substrate. The emitter 28 also includes the N diffusion region 29. Spacers, such as oxide spacers 32 and 34, are located on either side of the N.sup.+ polysilicon region 30. Two metal contacts 36 and 38 connect to the P.sup.+ base contact regions 24 and 26. A third metal contact 40 connects to the deep connector region 20 for contact with the N.sup.+ collector buried layer 14. A fourth metal contact 41 connects the surface to the emitter 28. Note that metal contacts 36, 38, 40 and 41 are formed in openings of an inter-layer-dielectric (ILD) layer 42.
The overall structure is an NPN transistor with N-type collector 16, P-type base 22 and N-type emitter 28. The buried N.sup.+ layer 14 and N.sup.+ deep connector 20 form a collector contact, whereas the P.sup.+ regions 24 and 26 form a base contact. Because the base contact regions do not connect directly to the P-type base regions 22, there is a parasitic resistor R.sub.b in series with the base of the BJT. The value of R.sub.b is determined by the P.sup.+ diffusion sheet resistance and the distance L.sub.1 between the base contact and the emitter. In general, P.sup.+ diffusion sheet resistance cannot be improved significantly without affecting device characteristics. The distance L.sub.1 depends on photo alignment tolerance between the polysilicon emitter and contact, and the metal contact process. Therefore R.sub.b can be reduced if L.sub.1 is shortened. However, a distance L.sub.2 is also needed to prevent contact of base metal regions 36 and 38 to the isolation regions, e.g. field oxide regions 18. The existence of L.sub.1 and L.sub.2 and the base contacts will enlarge the P.sup.+ diffusion regions 24 and 26 (to a depth of 0.3 .mu.m and a width of 1.4 .mu.m). Therefore, there exists a large base to collector capacitance C.sub.bc. Capacitance C.sub.bc will degrade BJT device performance greatly since it is located between the input node and the output node in the CE (common emitter) configuration of the BJT.
To improve the BJT characteristics, a first proposed BJT 10' with a self-aligned base contact is formed using a process as depicted in FIG. 2. Using conventional front end processes, the N.sup.+ layer 14 is formed on the substrate 12. Further, the N-type collector region 16 is formed and then the field oxide (FOX) regions 18 are formed on the substrate surface. The deep collector connector region 20 is then formed by diffusion or ion implantation into the N-type well 16. Next, the P base region 22 is formed by diffusion or ion implantation. Thereafter, the P.sup.+ polysilicon interconnect links 54 and 56 are formed. Specifically, the interconnect links 54 and 56 are formed by depositing a polysilicon layer, patterning the polysilicon layer using photolithography and then etching. The P.sup.+ base contact regions 24 and 26 are formed by out-diffusion from the P.sup.+ polysilicon interconnect links 54 and 56. This forms a self-aligned link from the P base 22, through the P.sup.+ base contact regions 24 and 26, and through the P.sup.+ polysilicon regions 54 and 56 to the base metal contacts 36 and 38 (which are formed after ILD deposition).
Next the emitter 28 is formed by depositing an N.sup.+ polysilicon layer and patterning this layer to form the N.sup.+ polysilicon emitter region 30. The N.sup.+ emitter region 29 is formed by out-diffusion from the N.sup.+ polysilicon region 30. After this, the ILD layer 42 is formed and patterned to enable formation of the metal contacts 36, 38, 40 and 41.
From these steps the BJT 10' with the self aligned base contact is formed. Because the P base 22 is connected using the P.sup.+ polysilicon regions 54 and 56, the P.sup.+ base contact regions 24 and 26 can be made smaller than the P.sup.+ base contact regions in the conventional device of FIG. 1. Thus, the collector-base capacitance C.sub.bc in the device 10' of FIG. 2 is smaller than C.sub.bc in the device 10 of FIG. 1. Parasitic resistance R.sub.b can also be reduced by the low resistance P.sup.+ polycide base connectors.
However, the device 10' of FIG. 2 still has certain deficiencies. First of all, because two polysilicon (polycide) processes are used to achieve the self-aligned BJT, the entire process complexity is increased. Secondly, the P.sup.+ base contact regions 24 and 26 are formed before a thermal cycle is used to form the N.sup.+ emitter region 29 by out-diffusion from the N.sup.+ polysilicon region 30. This thermal cycle will cause the P.sup.+ impurities in the P.sup.+ regions 24 and 26 to out-diffuse, thereby enlarging the size of the P.sup.+ regions 24 and 26. This in turn can cause N.sup.+ emitter region (region 29) to P.sup.+ base contact region (regions 24 and 26) junction leakage. In addition, C.sub.bc will be increased due to the increase in the size of the P.sup.+ regions 24 and 26.
Moreover, because the P.sup.+ base contact regions 24 and 26 are formed by out-diffusion from the P.sup.+ links 54 and 56, only polysilicon or polycide can be used for these links and this results in a large base interconnection resistance. Furthermore, since the emitter width (W.sub.E) is equal to the total diffusion area width (W.sub.1) minus the partial width of the two P.sup.+ polycide base connectors (W.sub.p1 +W.sub.p2) minus two times the spacer width (between the emitter 30 and P.sup.+ polycide base connectors 54 and 56), the emitter width cannot be easily controlled, adversely affecting BJT device characteristics.
To solve these issues a second proposed BJT 10" with a self-aligned base contact is formed using a process as depicted in FIG. 3. Using conventional front end processes, the N.sup.+ layer 14 is formed on the substrate 12. The N-type collector region 16 is formed and then the field oxide (FOX) regions 18 are formed on the substrate surface. The deep collector connector region 20 is then formed by diffusion or ion implantation into the N-type well 16. Thereafter, the base connector regions 54 and 56 and the emitter region 28 are formed by first depositing a polysilicon layer, patterning the polysilicon layer using photolithography and etching.
The distance W.sub.E is defined by the photolithographic process. The emitter region 28 includes the N.sup.+ polysilicon (polycide) region 30 formed on the surface of the substrate and the N.sup.+ diffusion region 29. Spacers, such as oxide spacers 32, are located on either side of the N.sup.+ polysilicon region 30. Impurities are thermally driven out of the emitter region 30 to form the N.sup.+ diffusion region 29 and out of the base contact regions 54 and 56 to form P.sup.+ diffusion areas 24 and 26, respectively. Two metal contacts 36 and 38 connect to the P.sup.+ base contact regions 24 and 26. A third metal contact 40 connects to the deep connector region 20 for contact with the N.sup.+ collector contact layer 14. A fourth metal contact 41 connects to the emitter 28. The metal contacts 36, 38, 40 and 41 are formed in openings of an ILD layer 42.
This polysilicon (polycide) process complexity is reduced as compared to the device of FIG. 2. However, some of the disadvantages, described above, remain. For instance, since the polysilicon (polycide) emitter 28 is patterned at the same time as the P.sup.+ polysilicon (polycide) base connectors 54 and 56, some spacing (W.sub.p) must be left between these two regions. For instance, if a 0.35 .mu.m BJT process is applied, then the resulting size of W.sub.p is approximately 0.4 .mu.m. Therefore, in addition to R.sub.b there is an additional base series resistor R.sub.b '. Note to that the P.sup.+ diffusion regions 24 and 26 will be enlarged due to the necessary spacing W.sub.p, which will increase C.sub.bc. In addition, the parasitic devices R.sub.b +R.sub.b ' and C.sub.bc are still too large to be used in high speed circuits.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.